The invention relates to a programmable non-volatile semiconductor memory cell of the type having an n-channel insulated gate field effect transistor comprising a gate electrode which is floating with respect to potential, is enclosed on all sides by an insulating material and which on its surface has electrodes which extend beyond the channel region of the insulated gate field effect transistor which channel region is arranged at the surface of a monocrystalline semiconductor substrate and which gate electrode is coupled capacitively by means of two electrode parts of different size via an insulated gate to respective programming electrodes, as known from the "1978 IEEE International Solid-State Circuits Conference, Digest of Technical Papers" (February, 1978), pp. 196 and 197. In this semiconductor memory cell there are provided two programming electrodes which, with the gate electrode which is floating with respect to potential, and consists of polycrystalline silicon, form two differently large capacitances, and with the dielectric thereof consisting of silicon oxide thermally grown on the gate elctrode, as may be concluded from the publication in conjunction with FIG. 2 thereof, in which erase characteristics relating to silicon oxides grown on monocrystalline and on polycrystalline silicon for serving as the dielectric for the capacitances, are confronted with one another. From FIG. 3 is results that the silicon oxide dielectric as grown on polycrystalline material have several times lower erase voltages than the one grown on monocrystalline silicon. This is deemed to be due to increased electric fields in the vicinity of the silicon grain borders.